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K6R1008V1B-C/B-L, K6R1008V1B-I/B-P
Document Title
Preliminary PRELIMINARY CMOS SRAM
128Kx8 Bit High Speed Static RAM(3.3V Operating), Revolutionary Pin out. Operated at Commercial and Industrial Temperature Ranges.
Revision History
Rev No. Rev. 0.0 Rev.1.0 History Initial release with Design Target. Release to Preliminary Data Sheet. 1.1. Replace Design Target to Preliminary. Release to Final Data Sheet. 2.1. Delete Preliminary. 2.2. Delete 32-SOJ-300 package. 2.3. Add Capacitive load of the test environment in A.C test load. 2.4. Change D.C characteristics. Previous spec. Changed spec. Items (8/10/12ns part) (8/10/12ns part) ICC 160/150/140mA 160/155/150mA ISB 30mA 50mA Change Standby and Data Retention Current for L-ver. Items Previous spec. Changed spec. ISB1 0.5mA 0.7mA IDR at 3.0V 0.4mA 0.5mA IDR at 2.0V 0.3mA 0.4mA Draft Data Apr. 1st, 1997 Jun. 1st, 1997 Remark Design Target Preliminary
Rev.2.0
Feb. 25th, 1998
Final
Rev. 2.1
Aug. 4th, 1998
Final
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any questions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
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Rev 2.1 August 1998
K6R1008V1B-C/B-L, K6R1008V1B-I/B-P
128K x 8 Bit High-Speed CMOS Static RAM(3.3V Operating)
FEATURES
* Fast Access Time 8,10,12ns(Max.) * Low Power Dissipation Standby (TTL) : 50mA(Max.) (CMOS) : 5mA(Max.) 0.7mA(Max.) - L-Ver. only Operating K6R1008V1B-8 : 160mA(Max.) K6R1008V1B-10 : 155mA(Max.) K6R1008V1B-12 : 150mA(Max.) * Single 3.30.3V Power Supply * TTL Compatible Inputs and Outputs * Fully Static Operation - No Clock or Refresh required * Three State Outputs * 2V Minimum Data Retention ; L-Ver. only * Center Power/Ground Pin Configuration * Standard Pin Configuration K6R1008V1B-J : 32-SOJ-400 K6R1008V1B-T : 32-TSOP2-400CF
Preliminary PRELIMINARY CMOS SRAM
GENERAL DESCRIPTION
The K6R1008V1B is a 1,048,576-bit high-speed Static Random Access Memory organized as 131,072 words by 8 bits. The K6R1008V1B uses 8 common input and output lines and has an output enable pin which operates faster than address access time at read cycle. The device is fabricated using SAMSUNGs advanced CMOS process and designed for highspeed circuit technology. It is particularly well suited for use in high-density high-speed system applications. The K6R1008V1B is packaged in a 400mil 32-pin plastic SOJ or TSOP2 forward.
ORDERING INFORMATION
K6R1008V1B-C8/C10/C12 K6R1008V1B-I8/I10/I12 Commercial Temp. Industrial Temp.
PIN CONFIGURATION(Top View)
A0 A1 1 2 3 4 5 6 7 8 9 32 A16 31 A15 30 A14 29 A13 28 OE 27 I/O8 26 I/O7
FUNCTIONAL BLOCK DIAGRAM
Clk Gen. Pre-Charge Circuit
A2 A3 CS I/O1 I/O2
A0 A1 A2 A3 A4 A5 A6 A7
Vcc
SOJ/ TSOP2
25 Vss 24 Vcc 23 I/O6 22 I/O5 21 A12 20 A11 19 A10 18 17 A9 A8
Row Select
Vss
Memory Array 256 Rows 512x8 Columns
I/O3 10 I/O4 11 WE A4 A5 12 13 14 15 16
I/O1~I/O8
Data Cont. CLK Gen.
I/O Circuit Column Select
A6 A7
PIN FUNCTION
A8 A9 A10 A11 A12 A13 A14 A15 A16
Pin Name A0 - A16
Pin Function Address Inputs Write Enable Chip Select Output Enable Data Inputs/Outputs Power(+3.3V) Ground No Connection
CS WE OE
WE CS OE I/O1 ~ I/O8 VCC VSS N.C
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Rev 2.1 August 1998
K6R1008V1B-C/B-L, K6R1008V1B-I/B-P
ABSOLUTE MAXIMUM RATINGS*
Parameter Voltage on Any Pin Relative to VSS Voltage on VCC Supply Relative to VSS Power Dissipation Storage Temperature Operating Temperature Commercial Industrial Symbol VIN, VOUT VCC PD TSTG TA TA Rating -0.5 to 4.6 -0.5 to 4.6 1.0 -65 to 150 0 to 70 -40 to 85
Preliminary PRELIMINARY CMOS SRAM
Unit V V W C C C
* Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS*(TA=0 to 70C)
Parameter Supply Voltage Ground Input High Voltage Input Low Voltage Symbol VCC VSS VIH VIL Min 3.0 0 2.0 -0.3** Typ 3.3 0 Max 3.6 0 VCC+0.3*** 0.8 Unit V V V V
* The above parameters are also guaranteed at industrial temperature range. ** VIL(Min) = -2.0V a.c(Pulse Width 6ns) for I 20mA. *** VIH(Max) = VCC + 2.0V a.c (Pulse Width 6ns) for I 20mA.
DC AND OPERATING CHARACTERISTICS*(TA=0 to 70C, Vcc=3.30.3V, unless otherwise specified)
Parameter Input Leakage Current Output Leakage Current Operating Current Symbol ILI ILO ICC Test Conditions VIN = VSS to VCC CS=VIH or OE=VIH or WE=VIL VOUT = VSS to VCC Min. Cycle, 100% Duty CS=VIL, VIN = VIH or VIL, IOUT=0mA Min. Cycle, CS=VIH f=0MHz, CS VCC-0.2V, VINVCC-0.2V or VIN0.2V IOL=8mA IOH=-4mA Normal L-Ver. 8ns 10ns 12ns Standby Current ISB ISB1 Min -2 -2 2.4 Max 2 2 160 155 150 50 5 0.7 0.4 V V mA mA Unit A A mA
Output Low Voltage Level Output High Voltage Level
VOL VOH
* The above parameters are also guaranteed at industrial temperature range.
CAPACITANCE*(TA=25C, f=1.0MHz)
Item Input/Output Capacitance Input Capacitance
* Capacitance is sampled and not 100% tested.
Symbol CI/O CIN
Test Conditions VI/O=0V VIN=0V
MIN -
Max 8 6
Unit pF pF
-3-
Rev 2.1 August 1998
K6R1008V1B-C/B-L, K6R1008V1B-I/B-P
AC CHARACTERISTICS(TA=0 to 70C, VCC=3.30.3V, unless otherwise noted.)
TEST CONDITIONS*
Parameter Input Pulse Levels Input Rise and Fall Times Input and Output timing Reference Levels Output Loads
* The above test conditions are also applied at industrial temperature range.
Preliminary PRELIMINARY CMOS SRAM
Value 0V to 3V 3ns 1.5V See below
Output Loads(A)
Output Loads(B) for tHZ, tLZ, tWHZ, tOW, tOLZ & tOHZ RL = 50 +3.3V
DOUT
VL = 1.5V
ZO = 50 30pF* DOUT 353
319
5pF*
* Capacitive Load consists of all components of the test environment.
* Including Scope and Jig Capacitance
READ CYCLE*
Parameter Read Cycle Time Address Access Time Chip Select to Output Output Enable to Valid Output Chip Enable to Low-Z Output Output Enable to Low-Z Output Chip Disable to High-Z Output Output Disable to High-Z Output Output Hold from Address Change Chip Selection to Power Up Time Chip Selection to Power DownTime Symbol tRC tAA tCO tOE tLZ tOLZ tHZ tOHZ tOH tPU tPD K6R1008V1B-8 Min 8 3 0 0 0 3 0 Max 8 8 4 4 4 8 K6R1008V1B-10 Min 10 3 0 0 0 3 0 Max 10 10 5 5 5 10 K6R1008V1B-12 Min 12 3 0 0 0 3 0 Max 12 12 6 6 6 12 Unit ns ns ns ns ns ns ns ns ns ns ns
* The above parameters are also guaranteed at industrial temperature range.
-4-
Rev 2.1 August 1998
K6R1008V1B-C/B-L, K6R1008V1B-I/B-P
WRITE CYCLE*
Parameter Write Cycle Time Chip Select to End of Write Address Set-up Time Address Valid to End of Write Write Pulse Width(OE High) Write Pulse Width(OE Low) Write Recovery Time Write to Output High-Z Data to Write Time Overlap Data Hold from Write Time End Write to Output Low-Z Symbol tWC tCW tAS tAW tWP tWP1 tWR tWHZ tDW tDH tOW K6R1008V1B-8 Min 8 6 0 6 6 8 0 0 4 0 3 Max 4 K6R1008V1B-10 Min 10 7 0 7 7 10 0 0 5 0 3 Max 5 -
Preliminary PRELIMINARY CMOS SRAM
K6R1008V1B-12 Min 12 8 0 8 8 12 0 0 6 0 3 Max 6 -
Unit ns ns ns ns ns ns ns ns ns ns ns
* The above parameters are also guaranteed at industrial temperature range.
TIMMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1)
Address tOH Data Out Previous Valid Data tAA Valid Data
(Address Controlled, CS=OE=VIL, WE=VIH)
tRC
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Rev 2.1 August 1998
K6R1008V1B-C/B-L, K6R1008V1B-I/B-P
TIMING WAVEFORM OF READ CYCLE(2)
(WE=VIH)
Preliminary PRELIMINARY CMOS SRAM
tRC Address tAA tCO tOE OE tOLZ Data out VCC Current ICC ISB tLZ(4,5) Valid Data tPU 50% tPD 50% tOH tOHZ tHZ(3,4,5)
CS
NOTES(READ CYCLE) 1. WE is high for read cycle. 2. All read cycle timing is referenced from the last valid address to the first transition address. 3. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit condition and are not referenced to VOH or VOL levels. 4. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device. 5. Transition is measured 200mV from steady state voltage with Load(B). This parameter is sampled and not 100% tested. 6. Device is continuously selected with CS=VIL. 7. Address valid prior to coincident with CS transition low. 8. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle.
TIMING WAVEFORM OF WRITE CYCLE(1)
(OE= Clock)
tWC Address tAW OE tCW(3) CS tAS(4) WE tDW Data in High-Z tOHZ(6) Data out High-Z(8) Valid Data tDH tWP(2) tWR(5)
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Rev 2.1 August 1998
K6R1008V1B-C/B-L, K6R1008V1B-I/B-P
TIMING WAVEFORM OF WRITE CYCLE(2)
(OE=Low Fixed)
Preliminary PRELIMINARY CMOS SRAM
tWC Address tAW tCW(3) CS tAS(4) WE tDW Data in High-Z tWHZ(6) Data out High-Z(8) Valid Data tOW
(10) (9)
tWR(5)
tWP1(2)
tDH
TIMING WAVEFORM OF WRITE CYCLE(3) (CS = Controlled)
tWC Address tAW tCW(3) CS tAS(4) WE tDW Data in tDH tWP(2) tWR(5)
High-Z
tLZ tWHZ(6)
Data Valid
High-Z
Data out
High-Z
High-Z(8)
NOTES(WRITE CYCLE) 1. All write cycle timing is referenced from the last valid address to the first transition address. 2. A write occurs during the overlap of a low CS and WE. A write begins at the latest transition CS going low and WE going low ; A write ends at the earliest transition CS going high or WE going high. tWP is measured from the beginning of write to the end of write. 3. tCW is measured from the later of CS going low to end of write. 4. tAS is measured from the address valid to the beginning of write. 5. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CS or WE going high. 6. If OE, CS and WE are in the Read Mode during this period, the I/O pins are in the output low-Z state. Inputs of opposite phase of the output must not be applied because bus contention can occur. 7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle. 8. If CS goes low simultaneously with WE going or after WE going low, the outputs remain high impedance state. 9. Dout is the read data of the new address. 10. When CS is low : I/O pins are in the output state. The input signals in the opposite phase leading to the output should not be applied.
-7-
Rev 2.1 August 1998
K6R1008V1B-C/B-L, K6R1008V1B-I/B-P
FUNCTIONAL DESCRIPTION
CS H L L L
* X means Dont Care.
Preliminary PRELIMINARY CMOS SRAM
I/O Pin High-Z High-Z DOUT DIN Supply Current ISB, ISB1 ICC ICC ICC
WE X H H L
OE X* H L X
Mode Not Select Output Disable Read Write
DATA RETENTION CHARACTERISTICS*(TA=0 to 70C)
Parameter VCC for Data Retention Data Retention Current Symbol VDR IDR Test Condition CSVCC-0.2V VCC=3.0V, CSVCC-0.2V VINVCC-0.2V or VIN0.2V VCC=2.0V, CSVCC-0.2V VINVCC-0.2V or VIN0.2V Data Retention Set-Up Time Recovery Time tSDR tRDR See Data Retention Wave form(below) Min. 2.0 Typ. Max. 3.6 0.5 Unit V mA
-
-
0.4
0 5
-
-
ns ms
* The above parameters are also guaranteed at industrial temperature range. Data Retention Characteristic is for L-ver only.
DATA RETENTION WAVE FORM
CS controlled
VCC 3.0V tSDR Data Retention Mode
tRDR
VIH VDR CSVCC - 0.2V
CS GND
-8-
Rev 2.1 August 1998
K6R1008V1B-C/B-L, K6R1008V1B-I/B-P
PACKAGE DIMENSIONS
32-SOJ-400
#32 #17
Preliminary PRELIMINARY CMOS SRAM
Units:millimeters/Inches
10.16 0.400
11.18 0.12 0.440 0.005
9.40 0.25 0.370 0.010
0.20 #1 21.36 MAX 0.841 20.95 0.12 0.825 0.005 ( 1.30 ) 0.051 ( 1.30 ) 0.051 0.43
+0.10 -0.05
#16 0.69 MIN 0.027
0.008
+0.10 -0.05 +0.004 -0.002
3.76 MAX 0.148
0.10 MAX 0.004
( 0.95 ) 0.0375
0.017 +0.004 -0.002
1.27 0.050
0.71
+0.10 -0.05
0.028 +0.004 -0.002
32-TSOP2-400CF
0~8 0.25 ( 0.010 ) #32 #17 0.45 ~0.75 0.018 ~ 0.030
11.76 0.20 0.463 0.008
10.16 0.400
#1 21.35 MAX 0.841 20.95 0.10 0.825 0.004
#16 0.15 +0.10 -0.05 0.006 +0.004 -0.002
( 0.50 ) 0.020
1.00 0.10 0.039 0.004 ( 0.95 ) 0.037 0.40 0.10 0.016 0.004 1.27 0.050 0.05 0.002MIN
1.20 0.047 MAX
0.10 MAX 0.004 MAX
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Rev 2.1 August 1998

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